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Task Responsible: Jorge Sousa
Sub-Tasks
Task responsible: Álvaro Combo
2012-01-09 The architecture of the firmware is now defined. An issue still exists regarding the availability of the WR PTP control software (not found on the WR SVN repository)
Task responsible: Rita Pereira
2012-01-09 The preliminary architecture of the card and FPGA code in now defined. Component assessment in progress.
Task responsible: João Fortunato?
2012-01-02 An assessment of the available 16-bit 10 MSPS serial ADCs from various manufacturers, found the more adequate ADC for this module (in terms of static and dynamic parameters, latency and footprint area) to be the Analog Devices AD7626 as well as the pin-to-pin compatible AD7625 (up to 6 MSPS for lower sampling frequency, lower cost requirements).
Task responsible: Alvaro Combo?
2012-01-09 No activities were performed yet.
Task responsible: Jorge Santos
To use the ITER prototype fast plant system controller for the development of the plasma position reflectometry case study for the data acquisition and algorithms
Task responsible: Álvaro Combo
Relevant for MW diagnostics on several existing tokamaks
Task responsible: João Fortunato, Bernardo Brotas
Digital Integrator based on the chopper ADC module for the ATCA-IO-PROCESSOR test-bench.
Tests shall assess the performance for long term integration.
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AMC_1GSPS_Clock.jpg No description | 319.55 kB | 15:25, 9 Jan 2012 | jsousa | Actions |