Description
Digital pulse processing (DPP) systems are known to have better performance than analog ones. DPP can synthesize almost any pulse response shape without the associated signal degradation which happens in a complex analog path.
This board contains high-speed transient recorders with auto-trigger functionality, used to digitize and store the detailed shape of pulses. Algorithms for the detection of pulse pile-up, Pulse Height Analysis, and, optionally, Pulse Shape Discrimination are implemented on the on-board FPGA, and can be applied to the digitized pulses for data reduction or real-time spectra monitoring.
Characteristics
-
ATCA board with eight acquisition channels per module;
-
Data transfer rate of up to 800 Mbyte/s over x4 PCI Express to the host processor.
-
A maximum sampling rate / resolution of 250 MSPS @ 13-bit, 400 MSPS @ 14-bit or 500 MSPS @ 12-bit depending on the ADC choice;
-
The channels can be paired for a higher sampling rate, respectively: 500, 800 or 1000 MSPS; the ENOB figure is then as low as ~10-bit;
-
Maximum pulse rate in excess of 5 Mpulse/s are attainable(e.g. 6.25 MSPS for 400 MSPS @64 sample/pulse) since there is no dead-time during data processing;
-
ENOB higher than11-bit (measured for energies from 4 MeV to 20 MeV);
-
2 Gbytes of local memory (DDR2) arranged as two memory modules, each one storing the acquired data of four ADC channels (256 Mbytes/channel);
-
Digitally programmable pulse level detection with configurable amount of pre-trigger and pos-trigger samples;
-
Optional programmable input voltage offset to configure for maximum signal amplitude on the analogue input (-1V to +1V @ 50 ohms);
-
Internall or external start trigger (in the front-panel);
-
Externally/internally clocked/triggered programmable time mark (1 ms nominal) to trigger the storage of the pulse counting value. The acquired pulse vector between two marks can be used to calculate lap spectra;
-
The local timestamp has a resolution as low as 1.25 ns and spans, at least, one day;
